1. Technical Field
The present disclosure relates to a semiconductor device included in, for example, an image processing apparatus to achieve improved safety of a vehicle and the like, a package, and a vehicle, and a vehicle and various electronic devices can provide improved performance when the semiconductor device and the package are mounted.
2. Description of the Related Art
Recently, increasing safety has been required for a vehicle. The safety and performance of a vehicle are improved by cameras (optical devices using, for example, visible light and infrared) attached to front and rear sides of the vehicle, and radars (using, for example, ultrasonic, laser, and milliwaves). In addition, for example, a HDMI (registered trademark) device is used in the field of in-vehicle communication with devices mounted on a vehicle, and the field of high speed communication with portable terminals.
A semiconductor device and a package according to the present disclosure are applicable to various electronic devices as well as a vehicle.
The safety and performance of a vehicle and various electronic devices can be improved by using the semiconductor device according to the present disclosure, and the package on which the semiconductor device is mounted.
FIG. 47 is a sectional view of an exemplary conventional signal processing semiconductor package. The following describes the conventional semiconductor package with reference to FIG. 47. FIG. 47 is a sectional view for description of an exemplary conventional plastic ball grid array (PBGA) semiconductor package. Conventional semiconductor package 1 includes semiconductor chip 2, substrate unit 3, wire 4 which electrically connects substrate unit 3 and semiconductor chip 2, and molding unit 5 which protects these components. Solder ball 6 is formed on one surface of substrate unit 3, and semiconductor package 1 can be mounted on a circuit board (not illustrated).
However, in such a conventional semiconductor device, when high-speed signal processing is performed, jitters cause a problem. Jitters are generated due to fluctuation of power-supply voltages referred to as Vdd and Vss (Vdd for drain voltage, and Vss for source voltage) inside a semiconductor.
It is conventionally disclosed that a laminated ceramic capacitor is included as a bypass capacitor in the package together with the semiconductor chip to improve a jitter characteristic. The laminated ceramic capacitor advantageously has a large capacity at low cost. In a semiconductor chip integrally including an analog circuit and a digital circuit, power division is required in some cases. The laminated ceramic capacitor needs to be disposed at each dividing position to achieve such a semiconductor chip in which power division is required.
However, when the semiconductor chip and the laminated ceramic capacitor are disposed on an identical surface, an increased mount area is needed, which is a problem. In addition, when the laminated ceramic capacitor is mounted by soldering, prevention of soldering re-melting in the following soldering reflow process needs to be provided. The laminated ceramic capacitor is disposed outside of the semiconductor chip and outside of a wire bonding region connected with the semiconductor chip. As a result, the semiconductor device has an increased projected area, which is another problem. When the projected area is increased, a circuit length between the semiconductor chip and the laminated ceramic capacitor is increased, equivalent series resistance (ESR) and equivalent series inductance (ESL) are increased, and a jitter value is increased. The jitter refers to fluctuation and disorder of a signal waveform in a time axial direction. When the jitter value is increased, for example, data error in a digital circuit is caused in some cases, and a signal quality in an analog circuit decreases in some cases.
It is disclosed to include a stacked capacitor using tape automated bonding (TAB) to solve such a problem. PTL 2 discloses that a capacitor achieved by insulating film 9 and metal foil 10 is included as a bypass capacitor on a bottom surface of the semiconductor chip in the package. More detailed description will be made below with reference to FIG. 48.
FIG. 48 is a sectional view of a semiconductor package including a conventional parallel plate capacitor achieved by an insulating film and a metal foil. In FIG. 48, reference sign 7 denotes a TAB. Semiconductor chip 2 is formed on one surface of TAB 7, and metal foil 10 is formed on the other surface of TAB 7 through insulating film 9. TAB 7, insulating film 9, and metal foil 10 are included in capacitor unit 11. Wires 4 electrically connect semiconductor chip 2 and lead frame 12, and TAB 7 and lead frame 12.
TAB 7 is a tape flexible circuit board. In a TAB tape, wiring achieved by copper wires formed by etching is provided on a film made of polyimide.
However, when capacitor unit 11 is formed by using TAB 7, it is difficult to satisfy characteristics required for a bypass capacitor. In addition, it is difficult to form a ceramic sinter film having a high dielectric constant. This is partly because it is difficult to perform high temperature processing at 400° C. or higher when the TAB tape is used. This is because a polyimide material used as the TAB tape is not resistant to a temperature of 400° C. or higher. In addition, when the TAB tape is used, a dielectric material used to form capacitor unit 11 is selected from a limited range of dielectric materials formed at lower than 400° C., in other words, at 300° C. or lower, which is a temperature threshold to which the TAB tape is resistant. As a result, insulating film 9 that can be formed on the surface of the TAB tape is mainly made of resin and thus has a low dielectric constant. As a result, it is often difficult to form a large-capacity bypass capacitor that is not degraded through high speed signal processing, and thus provides an effect of reducing variation of power-supply voltage.
FIG. 49 is a sectional view of a semiconductor package including a conventional capacitor obtained by forming a dielectric on a lead frame. In FIG. 49, it is disclosed to use, as the dielectric, for example, tantalum oxide (dielectric constant ε=20 to 27 approximately), BaTiO3 (ε=2000 approximately), SrTiO3 (ε=150 to 200), BaSrTiO3 (ε=200 to 450), and PbLaZrTiO3 (ε=750 to 4000), and to use, as the lead frame, for example, 42FN, 50FN, and kovar (PTL 2).
As described above, a conventional heat-resistant metal material cannot be used in place of the TAB to form a capacitor. For example, exemplary components of kovar (Kovar) are Ni of 29%, Co of 17%, Si of 0.2%, Mn of 0.3%, and Fe of 53.5%, in weight %. A main component of 42FN (also referred to as 42 alloy) is 42Ni—Fe (mass %), and a main component of 50FN is 50Ni—Fe (mass %). These metal materials, which have excellent thermal resistances, have such a problem that, when the materials are fabricated as a lead frame having a fine pattern and subjected to thermal processing at high temperatures of 300° C. or higher, 600° C. or higher, and 900° C. or higher, a fine part is likely to deform.
In other words, when a capacitor is formed on a heat-resistant metal plate shaped in a lead frame having a fine pattern through thermal processing at high temperatures of 300° C. or higher, and 400° C. or higher, a polyimide reinforced portion provided to prevent a dimensional change at a fine part becomes deformed and burnt during heating, resulting in a largely decreased dimensional accuracy of the lead frame.